Emulation Engineer (ONLY W2)

Description Position for an experienced FPGA (Emulation) model engineer to develop, integrate, verify and validate FPGA fast prototype models for the team The ideal candidate will demonstrate the following skills bull Team player, very proactive and self-motivated bull VerilogVHDL coding and verification bull RTL logic design bull Logic synthesis bull Working knowledge of logic design principles, powertiming effects bull Develop system level test suites suitable for execution on emulators. bull Develop emulation tools such as debugger and monitor features. bull Integration of acquired IP blocks into synthesized design Minimum Qualifications – BSEE – preferred MSEE – 5+ years of experience in bull ASIC (Logic RTL Design) experience back ground with experience in FPGA and Emulation model development bull FPGA prototyping, silicon verification and system validation bull Mapping complex SOC design into multi-FPGA platforms and hands on experience with such prototyping systems, e.g. Zebu, Veloce, HAPS 80, Palladium or equivalent bull Silicon verification, test plan development and execution – 3+ years of experience in bull Knowledge of RTL language (e.g. VHDL, Verilog), in-circuit emulation development and FPGA fast prototyping. bull Understanding of standard interfaces and bus protocols PCIUSBETHSPII2CPCI-ESPIAXIAMBA Preferred Qualifications – Familiar with Simics Model development for HybridVirtual Platform – System board designdebugging, RTL, lab equipment, e.g. oscilloscopes and logic analyzers – Familiar with pre-Silicon prototyping tools, flows and methodologies